1. Field of the Invention
The present invention relates to a semiconductor memory device having a redundancy system for memory cell failures.
2. Description of the Related Art
Since the number of bits used in a semiconductor memory device has increased remarkably in recent years, the semiconductor memory device should have a huge number of memory cells. In such a semiconductor memory device, for improving the access speed, all of the memory cells are usually divided into a plurality of blocks. The memory cells for one block constitute a memory cell group. As the number of memory cells is increased, the probability that failures occur in any memory cells is increased. Therefore, redundancy cells are provided in addition to regular memory cells. As a result, when a failure of the regular memory cell is found (hereinafter, a regular memory cell which is found to be a failure one is referred to as a failure memory cell), an access to a corresponding redundancy cell is substituted for an access to the failure memory cell. Thus, the production yield has been improved.
A conventional memory cell group selection circuit in the above-mentioned semiconductor memory device is shown in FIG. 4. For simplicity of the description, it is assumed that the memory cells are divided into four blocks and hence they constitute four memory cell groups 51 to 54. In the blocks corresponding to the memory cell groups 51 to 54, redundancy decoders 61 to 64 and memory cell group selection decoders 81 to 84 are provided, respectively.
A case of a normal access is described. An address signal which indicates a specific address of a memory cell to be accessed which is included in one of the memory cell groups is input into all of the memory cell group selection decoders 81-84. For example, it is assumed that the memory cell having the address indicated by the input address signal (hereinafter, such an address is referred to as an input address) is included in the memory cell group 51. The memory cell group selection decoder 81 in the same block decodes the input address, so as to select the memory cell group 51. Then, in the memory cell group 51 selected by the memory cell group selection decoder 81, a regular memory cell having the input address is accessed.
For example, when a failure memory cell is found in the memory cell group 51, the address of the failure memory cell is registered in the redundancy decoder 61 in the same block. After the registration, when the failure memory cell is to be accessed, the redundancy decoder 61 in which the address of the failure memory cell has been registered switches an enable signal (hereinafter, referred to as an ENB signal) to a high level. The memory cell group selection decoder 81 in the same block receives the high-level ENB signal and decodes the address of the failure memory cell, so as to select the memory cell group 51 in the corresponding block. In the memory cell group 51, a redundancy cell in the memory cell group 51 corresponding to the failure memory cell is actually accessed, instead of the failure memory cell.
FIG. 5 shows an exemplary structure of the redundancy decoder. Respective bit values of an input address which is input into the redundancy decoder are represented by A1 to A5. An address for a failure memory cell which is registered in the redundancy decoder is the address of the memory cell included in the memory cell group of the block to which the redundancy decoder belongs. In this example, an address of five bits A1-A5 "01110" for a failure memory cell is registered in the redundancy decoder. The number of bits of the address for a failure memory cell is not limited to five. One unit of the circuit shown in FIG. 5 is provided for one address to be registered.
A chip selection signal CE is commonly supplied to all the redundancy decoders in the respective blocks of the same chip. When the chip selection signal CE is set to be a low level, a chip including the redundancy decoder shown in FIG. 5 is selected. In the selected chip, a transistor 501 in each of the redundancy decoders i s turned on, and the level of the node 509 is pulled up to the level of the power supply 508. At this time, if transistors 505a-505f and 506 which are grounded are all turned off, the redundancy decoder supplies a high-level ENB signal to the memory cell group selection decoder in the same block via a signal line 507. If any of the transistors 505a-505f and 506 are turned on, the voltage of the node 509 is grounded. As a result, the redundancy decoder supplies a low-level ENB signal to the memory cell group selection decoder in the same block via the signal line 507. An ON-resistance of the transistor 501 is set to be sufficiently larger than those of the transistors 505a-505f and 506.
Now, a manner for registering the address A1-A5 "01110" of the failure memory cell is described. Each of the redundancy decoders is provided with a circuit for inputting big values and inverted bit values therefrom of the address to be registered. Corresponding fuses which are connected to signal lines for inputting the respective bit values are caused to blow, whereby the address is registered. When an address signal A1-A3 "011" is input, all of the transistors 505a-505f should be in the OFF state, in order to set the ENB signal at the high level. However, with the above configuration, the transistors 505b, 505c and 505e into which high-level address signals A1, A2 and A3 are input are in the ON state. Therefore, in order to disconnect the transistors 505b, 505c and 505e from the circuit, corresponding fuses 504b, 504c and 504e are caused to blow. As a result, even when the transistors 505b, 505c and 505e are in the ON state, the voltage of the node 509 is not grounded. When the address signal A4-A5 "10" is input, a value obtained by a NAND operation between A4 and A5 is input so that the transistor 506 can be in the OFF state. In this case, the bit values A4 and A5 of the address to be registered are fixed . As described above, the fuses are caused to blow so that all the grounded transistors except for the transistor 501 may be in the OFF state when the address signal indicative of the registered address is input. Thus, when the address signal indicative of the registered address is input, the high-level ENB signal can be output. The blow of the fuse is performed, for example, by a laser trimmer.
FIG. 6 shows an exemplary configuration of the memory cell group selection decoder and an exemplary configuration of the memory cell group in the same block as the memory cell group selection decoder. The reference numeral 601 denotes part of the memory cell group selection decoder, and 602 the memory cell group. As an example, it is assumed that a five-bit address A1-A5 "01110" has been registered as an address of a failure memory cell in a redundancy decoder in the same block. The number of bits of the address for a failure memory cell is not limited to five. One unit of the part 601 of the memory cell group selection decoder is required for one registered address. An ENB signal from the redundancy decoder in the same block is supplied to the memory cell group selection decoder and the memory cell group 602 via a signal line 616. In this example case, a single address has been registered, so that a single unit of the part 601 is required in the memory cell group selection decoder. In other words, in this example, the part 601 corresponds to the memory cell group selection decoder (for example, 81), so that the part 601 is hereinafter referred to as the memory cell group selection decoder 601.
A case where a high-level ENB signal is supplied from the redundancy decoder when an address signal indicative of the registered address is input into the memory cell group selection decoder 601 is considered. In this case, an inverter 605 supplies a low-level signal to a plurality of NAND gates 612 in the memory cell group 602. When one of a plurality of row decoders 611 in the memory cell group 602 is selected, the selected row decoder 611 supplies a high-level signal to the NAND gate 612 to which the selected row decoder 611 is connected. The number of the row decoders 611 is, for example, 128 in one memory cell group 602. The output of the inverter 605 is at a low level, so that the output of an inverter 613 corresponding to the selected row decoder 611 is also at a low level. During when the output of the inverter 613 is at the low level, memory cells in a memory array 614 cannot be accessed.
In the above case, the redundancy decoder supplies a high-level ENB signal to a plurality of NAND gates 607 in the memory cell group 602 via the signal line 616. One of a plurality of row decoders 606 in the memory cell group 602 is selected. The selected row decoder 606 supplies a high-level signal to the NAND gate 607 to which the selected row decoder 606 is connected. The number of the row decoders 606 is, for example, 128 in one memory cell group 602. The ENB signal supplied to the memory cell group 602 is at the high level, so that the output of an inverter 608 corresponding to the selected row decoder 606 is also at a high level. When the output of the inverter 608 is at the high level, redundancy cells 610.sub.1 -610.sub.n in a redundancy memory array 609 can be selected. The selected redundancy cells 610.sub.1 -610.sub.n are a row of redundancy memory cells which are controlled by the selected row decoder 606. The number of the redundancy cells 610.sub.1 -610.sub.n in one row is, for example, 64 (n= 64). Thereafter, one cell to be accessed is selected among the row of redundancy cells 610.sub.1 -610.sub.n.
Next, another case where a low-level ENB signal is supplied from the redundancy decoder when an address signal indicative of the registered address is input into the memory cell group selection decoder 601 is considered. In this case, the output of the inverter 605 is at a high level. When one of the row decoders 611 is selected, the output of the inverter 613 corresponding to the selected row decoder 611 is at a high level. During when the output of the inverter 613 is at the high level, memory cells 615.sub.1 -615.sub.n in the memory array 614 can be selected. The access method to the memory cell in the memory array 614 is the same as that to the redundancy cell in the redundancy memory array 609. Also, in the memory array 614, for example, 64 memory cells 615.sub.1 -615.sub.64 are connected in a row (n=64).
In the above case, the redundancy decoder supplies a low-level ENB signal to the plurality of NAND gates 607 in the memory cell group 602 via the signal line 616. One of the plurality of row decoders 606 is selected. The output of the inverter 608 corresponding to the selected row decoder 606 is at a low level. Therefore, the redundancy cells in the redundancy memory array 609 cannot be accessed.
As described above, in the conventional semiconductor memory device, when any one of the memory cell groups 51-54 has any failure memory cell, the address of the failure memory cell is registered in the corresponding one of the redundancy decoders 61-64 in the same block, whereby the access to a redundancy cell provided in the corresponding one of the memory cell groups 51-54 in the same block is substituted for the access to the failure memory cell.
In some cases, for example, when a lot of failure memory cells occur only in the memory cell group 51, the number of the failure memory cells sometimes exceeds the number of redundancy cells provided in the memory cell group 51. However, in the redundancy decoder 61 as shown in FIG. 4, an address of a failure memory cell included in its memory cell group 51 of the same block can only be registered in order to substitute a redundancy cell provided in the memory cell group 51 for the failure memory cell. Therefore, even if there are unused redundancy cells in the other memory cell groups 52-54, it is impossible to substitute any one of the unused redundancy cells in the other memory cell groups 52-54 for the failure memory cell in the memory cell group 51.
Thus, in the conventional semiconductor memory device, an address of a failure memory cell included in a memory cell group can be registered only in a corresponding redundancy decoder in the same block. As a result, when a lot of failure memory cells occur in a memory cell group of a certain block, unused redundancy cells in memory cell groups of the other blocks, if any, cannot be utilized, which causes a problem in that such a semiconductor memory device is considered to be a defective.